A decoder circuit is typically required in order to implement both read-only-memories (ROMs) and random-access-memories (RAMs). The memory generally includes 2.sup.N words of storage which are addressed by an input address of N bits. The words stored by the memory are arranged in rows and a decoder circuit responsive to the input address is used to select the appropriate row. The decoder circuit is generally fabricated on the same monolithic integrated circuit chip which contains the storage elements of the memory. Therefore, the chip area required by the decoder circuit directly impacts the overall die size of the integrated circuit. It is well known that integrated circuits having a smaller die size have correspondingly higher processing yields which result in lower overall chip costs. Those skilled in the art will appreciate that a decoder circuit suitable for integrated circuit implementation and having a higher circuit density is a significant improvement over the prior art.